Code generation tool for control and status registers

Ansible Service Broker

Control and status register code generator toolchain

Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.

THIS REPO IS MIGRATING: https://github.com/automationbroker/apb

The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB. Read and write transfers on the AHB are converted into equivalent transfers on the APB.

Parameterised Asynchronous AHB3-Lite to APB4 Bridge.

Verification IP for AMBA APB Protocol

APB master and slave developed in RTL.

This repo contains a collection of Verilog+System Verilog+RTL+UVM+Protocols Projects

To design test bench of the APB protocol

Flaws' APB Reloaded Config

General Purpose IO with APB4 interface

Common SystemVerilog RTL modules for RgGen

APB4 Multiplexor

APB verification using UVM

A repository of example ansible-playbook bundles. THIS REPO IS DEPRECATED. Please look at https://github.com/ansibleplaybookbundle/ For updated examples.

This is my hobby project, which contain my rsic-v core and my convolutional layer with AMBA bus

APB CSS (Atomic Parts Base CSS) + JavaScript framework.

UVM-based functional verification of an APB-based UART Master Core RTL. Includes multi-agent environment, assertions, coverage collection, and multiple test scenarios (full/half duplex, parity, framing, timeout errors) achieving 100% functional coverage and protocol compliance.