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Pull requests: gem5/gem5

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Pull requests list

Adding the memory interfaces for the lpddr5 into the gem5 memory comp…
#3211 opened Jun 7, 2026 by sriramster Loading…
misc: Add GitHub Agentic Workflow for diagnosing test failures
#3210 opened Jun 6, 2026 by erin-le Contributor • Draft
mem-cache: Add profiling statistics to replacement policy
#3209 opened Jun 5, 2026 by HirunaVishwamith Loading…
9
dev: refactor PciUpstream to be a C++ interface dev General gem5 development code. Found in "src/dev"
#3208 opened Jun 4, 2026 by clemdiep Contributor Loading…
9
sim: fix false positive warning in sim/serialize.cc sim General gem5 Simulation Components
#3207 opened Jun 4, 2026 by OmeletWithoutEgg Loading…
2
dev: Expose serial terminal listen address to Python dev General gem5 development code. Found in "src/dev"
#3205 opened Jun 3, 2026 by OmeletWithoutEgg Loading…
4
misc,util-m5,ext-testlib: add color to panics/warnings/infos ext-testlib The gem5 testlib code. Found in "ext/testlib" misc Anything outside of the current labeling categories util-m5 gem5's m5 CLI and library. Found in "util/m5"
#3204 opened Jun 2, 2026 by blokyk Loading…
1
mem-cache: Fix cache block movement logic mem-cache Classic caches and coherence
#3203 opened Jun 2, 2026 by xcf-t • Draft
1
mem-ruby: Add Cbusy handling logic to the TlmGenerator mem-ruby Ruby caches, structures, and protocols
#3202 opened Jun 2, 2026 by giactra Contributor Loading…
build: CMake build infrastructure (1/6) misc Anything outside of the current labeling categories scons Scons. gem5's Build System
#3194 opened May 23, 2026 by RushabPatil • Draft
2
cpu-o3: O3 CPU inter-stage unblock signal causes 1-cycle bubble due to propagation delay cpu-o3 gem5's Out-Of-Order CPU
#3191 opened May 21, 2026 by zhongchengyong Contributor Loading…
1
@BobbyRBruce
1
build(deps): bump idna from 3.7 to 3.15 in /util/gem5-resources-manager dependencies Pull requests that update a dependency file python gem5's Python SimObject wrapping and infrastructure
#3187 opened May 20, 2026 by dependabot Bot Loading…
@erin-le
misc: Implement remaining armv82 crypto instructions arch-arm The ARM ISA configs gem5's Preprepared Python Configuration scripts. Typically found in "configs" cpu General gem5 CPU code (e.g., `BaseCPU`)
#3182 opened May 19, 2026 by giactra Contributor Loading…
sim: runtime debug flags toggle via SIGRTMIN+1 sim General gem5 Simulation Components
#3181 opened May 19, 2026 by polpetras Loading…
[pre-commit.ci] pre-commit autoupdate misc Anything outside of the current labeling categories
#3179 opened May 18, 2026 by pre-commit-ci Bot Loading…
@erin-le
configs: Add support for CHI-TLM writes in the example library configs gem5's Preprepared Python Configuration scripts. Typically found in "configs"
#3177 opened May 17, 2026 by giactra Contributor Loading…
dev-virtio,configs-arm: Add 9P directory rootfs support configs gem5's Preprepared Python Configuration scripts. Typically found in "configs" dev-virtio gem5 virtio development code. Found in "src/dev/virtio"
#3176 opened May 15, 2026 by lionkov Loading…
1
sim,mem: Add zstd/raw as backing store compression options mem General Memory Systems (e.g., XBar, Packet) sim General gem5 Simulation Components
#3174 opened May 15, 2026 by hnpl Contributor Loading…
25
arch-x86: Fix CVTSI2SS REX.W source width arch-x86 The X86 ISA
#3171 opened May 14, 2026 by SofanHe Loading…
2
arch-riscv: Fix segfault in masked vector strided loads arch-riscv The RISC-V ISA
#3162 opened May 11, 2026 by amatabsc Contributor Loading…
1
cpu: Fix O3 misc-reg commit visibility hazard cpu General gem5 CPU code (e.g., `BaseCPU`)
#3158 opened May 9, 2026 by tsyw Loading…
1
20
misc: Add labeler workflow to automatically label PRs based on files changed misc Anything outside of the current labeling categories
#3151 opened May 8, 2026 by erin-le Contributor Loading…
5
gpu-compute: Emulate copy aligned BLIT kernels gpu gem5's GPU Simulation infrastructure gpu-compute gem5's GPU Compute Code
#3149 opened May 7, 2026 by abmerop Member Loading…
3
cpu-o3: Early retire prefetches after issuing memory requests cpu-o3 gem5's Out-Of-Order CPU
#3148 opened May 7, 2026 by pxk27 Loading…
1
5
configs,mem-ruby: extend CHI for SimpleNetwork configs gem5's Preprepared Python Configuration scripts. Typically found in "configs" mem-ruby Ruby caches, structures, and protocols
#3146 opened May 6, 2026 by giactra Contributor Loading…
8
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